Telecom operators and military/defense applications (e.g., UAVs) prefer to offload compute-intensive cryptographic processing to FPGA-based cryptographic accelerators over fixed-function ASICs for reconfigurability and short deployment cycles. The state-of-the-art FPGA-based cryptographic accelerators are designed either for high throughput or power efficiency. We propose FlexMesh, a programmable, dynamically reconfigurable, and size-aware framework for 5G/6G cryptographic primitives using FPGAs. By leveraging FPGA adaptability, our approach supports emerging algorithms and optimizes performance across dynamic workloads, helping future-proof cryptographic acceleration for next-generation networks.